With sophisticated architecture and advanced technology, KNiulink provide LPDDR4/4x IP solution with high performance and low power. In advanced process nodes, KNiulink could offer both controller and PHY IPs. In architecture, it supports Multiport AMBA AXI interface, configurable port number and support asynchronous or synchronous AXI port. For PHY interface, it will integrate DFI compatible design. One de-skew PLL is embedded inside the PHY to improve jitter performance.

 With sophisticated architecture and advanced technology, KNiulink provide LPDDR3 IP solution with high performance and low power. In advanced process nodes, KNiulink could offer both controller and PHY IPs. In architecture, it supports Multiport AMBA AXI interface, configurable port number and support asynchronous or synchronous AXI port. For PHY interface, it will integrate DFI compatible design. One de-skew PLL is embedded inside the PHY to improve jitter performance.

 With sophisticated architecture and advanced technology, KNiulink provide LPDDR2 IP solution with high performance and low power. In advanced process nodes, KNiulink could offer both controller and PHY IPs. In architecture, it supports Multiport AMBA AXI interface, configurable port number and support asynchronous or synchronous AXI port. For PHY interface, it will integrate DFI compatible design. One de-skew PLL is embedded inside the PHY to improve jitter performance.

 With sophisticated architecture and advanced technology, KNiulink provide DDR5 IP solution with high performance and low power. In advanced process nodes, KNiulink could offer both controller and PHY IPs. In architecture, it supports Multiport AMBA AXI interface, configurable port number and support asynchronous or synchronous AXI port. For PHY interface, it will integrate DFI compatible design. One de-skew PLL is embedded inside the PHY to improve jitter performance.

 With sophisticated architecture and advanced technology, KNiulink provide DDR4 IP solution with high performance and low power. In advanced process nodes, KNiulink could offer both controller and PHY IPs. In architecture, it supports Multiport AMBA AXI interface, configurable port number and support asynchronous or synchronous AXI port. For PHY interface, it will integrate DFI compatible design. One de-skew PLL is embedded inside the PHY to improve jitter performance.

 With sophisticated architecture and advanced technology, KNiulink provide DDR3 IP solution with high performance and low power. In advanced process nodes, KNiulink could offer both controller and PHY IPs. In architecture, it supports Multiport AMBA AXI interface, configurable port number and support asynchronous or synchronous AXI port. For PHY interface, it will integrate DFI compatible design. One de-skew PLL is embedded inside the PHY to improve jitter performance.

 This IP is a high-speed LVDS (Low-Voltage Differential Signaling) transceiver supporting multi-channel joint. The LVDS TX & RX IP is specified for operation over the industrial temperature range. This IP operates from 3.3V/1.1V supply and works with 992Mbps data rate. It’s compatible with ANSI/TIA/EIA-644-A (LVDS) Standard.

 With sophisticated architecture and advanced technology, KNiulink USB3.1 transceiver IP with PMA and PCS layer is designed for low power and high performance application. It is highly configurable and can be tightly integrated with the user logic or SOC resources. Data rate for Gen 1 physical layer is 5Gbps, and data rate for Gen 2 physical layer is 10Gbps.

 With sophisticated architecture and advanced technology, KNiulink SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and high performance application. It is highly configurable and can be tightly integrated with the user logic or SOC resources; it can support SATA protocol with data rate 1.5/3/6Gbps, and SAS protocol with data rate 1.5/3/6/12Gbps.

 With sophisticated architecture and advanced technology, KNiulink SerDes PHY IP with PMA and PCS layer is designed for low power and high performance application. This SerDes PHY IP diagram is shown as following figure for a single channel. PCS layer and PMA layer include RX, TX and a common lane. The interfaces between users and IP are PIPE interface. All the control and configuration bits of the SerDes PHY IP are assigned in register map at PCS side and can be accessed through JTAG interface and register access port.

 This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications. It is designed for low power and high-performance application. This IP supports data rate up to 2.5Gbps.

 56G SerDes IP core supports PAM4 signaling in the range of 25.0-60.0 Gbps using full-rate and half-rate modes with scrambled data. Non-return-to-zero (NRZ) signaling is supported in the range of 5.0-30.0 Gbps using full, half, and quarter-rate modes. Either scrambled or block coded (for example, 8B/10B) data is supported for 5.0-12.5 Gbps in NRZ mode. However, scrambled data is required for data rates greater than 12.5 Gbps. The 56G SerDes IP cores are intended for use as a chip-to-chip or a card-to-card connection mechanism.

 With sophisticated architecture and advanced technology, JESD204B /204C IP with PHY and MAC layer is designed for low power and high performance application. It is fully compatible with JESD204B/204C specification, and supports link rate up to 25Gbps per lane. Take JESD204B TX IP as an example, which assembles the parallel data from the ADCs into frames and uses 8b/10b encoding, as well as optional scrambling, to form serial output data. For the MAC side, it has the transport layer, which handles packing the data into the JESD204B frames. Besides, the data link layer is responsible for the low level functions of passing data across the link. For the PMA side, it has four lanes and a common block.

RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture. The architecture addresses the need for faster bus speeds in an intra-system interconnect for microprocessors, digital signal processors and communications. RapidIO interconnect architecture is partitioned into a layered hierarchy of specifications which includes Logical, Common Transport and Physical layers, in which the Physical layer defines the interface between two devices and the packet transport mechanism, flow control and electrical characteristics. KNiulink RapidIO PHY offers the physical layer specification solution as defined in the RapidIO Specification Rev 4.0/3.1/2.2. The IP supports four-lane running at different transmission speeds up to 6.25/ 10.3125/25.78125Gbps. 

 With sophisticated architecture and advanced technology, KNiulink multi-mode transceiver IP with PMA and PCS layer is designed for low power and high performance application. It is highly configurable and can be tightly integrated with the user logic or SOC resources; it can support a wide variety of serial data transmission protocols with link rate up to 25/28/32Gbps.